Design of an Efficient Architecture for Advanced Encryption Standard Algorithm Using Systolic Structures

This Paper presents a systolic architecture for Advanced Encryption standard (AES). Use of systolic architecture has improved the hardware complexity and the rate of encryption/decryption. Similarities of encryption and decryption are used to provide a high performance using an efficient architecture. The efficiency of the design is quite high due to use of short and balanced combinational paths in the design. The encryption or decryption rate is 3.2-Bits per clock-cycle and due to the use of pipelined systolic architecture and balanced combinational paths maximum clock frequency for the design is quite high.